The present invention relates to a method for decoding a received biphase-coded signal, the data recovered being selected in a logic circuit and then being fed to a shift register, and to a facility or apparatus for carrying out this method and to the application of the method.
For the transmission of data, biphase line codes (also called frequency shift keying or phase shift keying) are used such as biphase-level, biphase-mark, biphase-space and others (see Linear Interface Data Book, Fairchild Camera and Instr. Corp., California, U.S.A., 1978, p. 10-42, FIG. 4-21), the line signals of which have a specified mean value and good clock transmmission characteristics.
Decoding facilities are known (John E. McNamara, Technical Aspects of Data Communication, 1977, by Digital Equipment Corporation, U.S.A., p. 5, FIG. 1-3) which are based on sampling the received signal within each data bit period.
In synchronous data transmission (uninterrupted data stream without bit synchronization characters), the clock for the sampling is obtained from the received signal.
In asynchronous data transmission, the sampling times for the n bits between start and stop character are located at precisely defined intervals away from the first edge of a start character. These intervals are determined by a digital counter which is started by the start character. In this arrangement, the counting rate is 16 times higher than the clock frequency of the data transmission in order to guarantee reliable sampling.
Such methods have the basic disadvantage that the frequency limit is 8-32 times lower than would be permitted by the semiconductor technology used in each case. The reason for this is found in the digital counters used which run 8-32 times faster. In addition, the number of bits between the start and stop character is normally limited to 8-16 bits. This is due to the fact that the determination of the sampling times becomes increasingly inaccurate with an increasing number of bits transmitted since in practice the counting rate is not an exact multiple of the clock frequency.